The present invention relates to a semiconductor device and more particularly to a semiconductor device with a microcomputer chip and plural memory chips mounted thereon.
According to a known technique (see, for example, Patent Literature 1), plural memory chips each having pads arranged on plural sides are stacked and further a microcomputer chip is stacked on those memory chips to configure a system.
According to another known technique (see, for example, Patent Literature 2), first electrode pads formed on a main surface of a semiconductor chip, as well as first bonding pads and first central bonding pads formed in an upper region with respect to the main surface of the semiconductor chip, are coupled together in one-to-one correspondence by a first re-wiring layer, and second electrode pads formed on the main surface of the semiconductor chip, as well s second bonding pads and second central bonding pads formed in an upper region with respect to the main surface of the semiconductor chip are coupled together in one-to-one correspondence by a second re-wiring layer.
[Patent Literature 1]
Japanese Patent Laid-Open Publication No. 2005-286126
[Patent Literature 2]
Japanese Patent Laid-Open Publication No. 2005-191213